Phase locked loops are an essential building block of most digital and mixed-signal integrated circuits. Much effort has been dedicated to develop a testing technique for phase locked loops in integrated circuits.
Various testing techniques are known. For instance, testing techniques may operate through a synchronous digital tester or mixed-signal tester. Such techniques may be complex to program, require high precision in on-the-fly timing changes, and involve significant test times. These difficulties often reduce the testing operation to a simple check that a PLL is able to achieve phase lock.
Built-in self-test (BIST) techniques are also generally known that make use of on-chip digital test circuitry, implemented in the typical digital ASIC design flow, i.e., design capture at the register transfer level in an HDL (Hardware Design Language), followed by logic synthesis and automatic layout. The test circuitry usually comprises a gated binary counter for measuring the phase of the PLL with respect to a known frequency. The measurements are then transferred to a tool external to the chip for analysis. A test access port (TAP) is used for test control and observation of measurement results. Such control and observation functions can be performed for instance through a personal computer connected through its parallel port.
Scan based built-in self-test is an important technique for testing large and complex circuits. The scan-based BIST schemes, which rely on scan design for testability, use linear feedback shift registers (LFSRs) as pseudo-random pattern generators, and employ multiple-input shift registers (MISRs) as test response compactors. In scan based BIST the generators shift the sequences into the scan chains serially. By “scan chain” a serial organization of scan elements is meant wherein the first element of the chain is at a device input and the last element of the chain is at a device output. Devices may use single or multiple scan chains to capture all of the scannable nodes.
BIST techniques and circuitry examples are described for instance in the publication “BIST for Phase-Locked Loops in Digital Applications”, S. Sunter and A. Roy, ITC International Test Conference Proceedings 199, p. 532.
Virtually all structural logic test methods, and BIST techniques in particular, are based on a full scan infrastructure. That is, all storage elements (flip-flops or latches) are connected together to form several scan chains so that in a test mode, data can be serially scanned into and out of these storage elements. Applying a test pattern includes scanning the pattern data, applying one or more functional clock cycles, and then scanning out the captured response data.
The problems that arise when testing PLLs through BIST techniques are essentially due to difficulties in generating the stimulus to run the BIST test approaches. So far, the following steps are generally followed: programming the TAP with a parallel scan mode instruction; re-programming the TAP with an instruction to assert a signal indicating the BIST testing of PLL (i.e., asserting a tst_pllbist signal), then the counter counts; waiting for the counter to stabilize; sending a pulse to the counter reset pin to bring to zero the counter; waiting a few milliseconds for the counter to count; and re-programming the TAP with a parallel scan mode instruction to close the counter gate.
Such a sequence for stimulus generation is quite complicated even if software features as macrotest/pattern mapping can be used to generate a WGL (Waveform Generation Language) file which contains the scan chain load of the values necessary to program the PLLs, followed by a scan chain unload of the expected values in the counters.
Further, this approach has an appreciable likelihood of being affected by errors. There is no mechanism, indeed, that may prevent the programmed PLL values from changing. Thus, if the same clock signal is used to clock both the PLL and the logic surrounding it, the programmed value could get corrupted.
Additionally, the PLL operating period during the test is not very accurate since it is determined by programming the TAP port with a different instruction from the run test instruction (Runbist instruction), so that the occurrence of the deassertion of the test signal (i.e., tst_pllbist signal de-asserted) closing the measurement window is not very clear.